5.1 Description of tools used for GenExec module
 

5.1.1 Caml

Programming languages are called functional, when the way to structure your programs is the use of functions, which  are then called from a control structure called functional application. We would like to have the way functions are written similar to the mathematical functions.  Mathematical functions can be composed and this composition is also a function. Caml respects this way of writing a function, but it also allows us to use non-functional programming styles. So Caml is functional language, but not purely functional.

Caml is developed and distributed by INRIA (the main French research institute for computer science), since 1984. It is freely available for Unix, PC or Macintosh.

There exist two flavors of Caml: Caml Light and Objective Caml.Caml Light is merely a subset of Objective Caml, especially designed for teaching and learning the art of programming.
In addition to the Caml Light's core language, Objective Caml features a powerful modules system, full support to object-oriented paradigm, and an optimizing compiler.

If you want more information regarding Caml you can check the internet site
http://caml.inria.fr/
 

5.1.2 VHDL

VHDL is a language for describing digital electronic systems. It came out of US government Very High Speed Integrated Circuits (VHSIC) program. In the course of this program it became clear that there was a need for standard language for describing the structure and function of integrated circuits. Because of that need the VHSIC Hardware Description Language (VHDL) was developed and in time
adopted as a standard.

VHDL is designed to fill a number of needs in the design process. First, it allows description of the structure of a design, that is how it is decomposed into sub-designs and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before
it being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.

5.1.3 m4 macro processor

With macro processor you can easyly use the same structure for different implementations. Different implementations depends on definition of macros in the library file. Basically this only replace a string in file with a definition in the library file. Let we see an example of utilizing macro code.
For example we take a line in macro file like:

                     EXAMPLEMACRO(dotp,6)

Then lets suppose that we have two library files. In the first example we have:

                    define(`EXAMPLEMACRO',Frontier $1 is repeated $2 times.)

In the second example we have definition of macro like this:

                    define(`EXAMPLEMACRO',$2 is defactorizing factor of frontier $1.)

If you compile the statement with the first library, the output will look like
this:

                    Frontier dotp is repeated 6 times.

and if you compile the same line with library definition from the second example you get the following result:

                    6 is defactorizing factor of frontier dotp
 

With this simple example you can see, that we didn't change the m4 file. We just used different definition library for the same macro and the result was different. So with such approach you can generate m4 file and then it depends which code you want you just use appropriate library. So if you would like to synthetize VHDL code you use library with definitions of macros for VHDL. So m4
code is independent of hardware you wish to synthetize code for.
 

5.2 Structure of VHDL file

On figure 5.1 you can see how does a structure of VHDL file looks like.

Digital system can be described as a module with inputs and outputs. You can see this on Figure 5.2. System F has two input ports A and B and one output port O. This is called entity of the system. So in entity section of VHDL code there is description of every input and output port that system use to
communicate with other systems.
 
 

One way to describe the function which module performs is to describe the composition of the module of sub-modules as seen on Figure 5.3. Each of this sub-modules is instance of the entity which is defined in separate file. Ports of the instances are connected internally using internal signals. This kind of description is called structural description. Each of the sub-modules can also have sub-modules and is described in some other file.

The module which is at the bottom of the hierarchy cannot be described structurally. In this case we describe the behaviour of module with the function this module will perform. Let say that we want to describe the behaviour of sub-module K on Figure 5.3 in following way: output O is a sum of input ports A and B.

We would do it like this in VHDL:

                                 O<=A+B;

In our project we will use structural description for frontiers ( as seen on Figure 5.3) and behavioural description for operators. Operators such as Join, Fork etc. described in section 2.2 are written in separate VHDL files where their behavior is described. Then the frontiers has operators and subfrontiers defined as components (structural description). After this we have to define internal signals, which are used for interconnections of components and connection of components to entity. And
finally we have to map every component.
 

5.3 Structure of GenExec module

Module is written in Caml. At the beginning I defined some functions which are useful later for adding and replacing text in the file.

Then there is main function called print frontier. This function is recursive, which means that this function is called from within itself. That is the way to apply this function to all the frontiers from outter most to the inner most. In this function first we create file with the name of the frontier. Then we
define all of the operators and subfrontiers which belongs to this frontier.

After this is done we place control unit. Then it makes interconnections between operators and subfrontiers and also connections to the entity. This is done by the use of FDFG. After we  have the FDFG defined in file we use FNG to establish interconnections between control units of different frontiers. at the end there is done definition of component of subfrontiers.

You can see printout of GenExec module in appendix A

5.4 Example of generation and simulation of VHDL

First we draw graph of the application. In our case you can see this graph on
Figures 5.4, 5.5, 5.6. We draw this with help of SynDEx.

You can see the output of GenExec module in appendix B.

You can see the VHDL code generated from GenExec module and compiled from m4
file in appendix C

Results of simulation can be seen on this figure.